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1 datasheet wide v in 150ma synchronous buck regulator ISL85412 the ISL85412 is a 150ma synchronous buck regulator with an input range of 3.5v to 40v. it provides an easy to use, high efficiency low bom count solution for a variety of applications. the ISL85412 integrates both high-side and low-side nmos fets and features a pfm mode fo r improved efficiency at light loads. this feature can be disabled if forced pwm mode is desired. the part switches at a default frequency of 700khz. by integrating both nmos devices and providing internal configuration, minimal external components are required, reducing bom count and complexity of design. with the wide v in range and reduced bom, the part provides an easy to implement design solution for a variety of applications while giving superior performance. it will provide a very robust design for high voltage industrial applications as well as an efficient solution for battery powered applications. the part is available in a small pb-free 3mmx3mm tdfn plastic package with an operat ion junction temperature range of -40c to +125c. related literature ? an1929 , ?isl85413eval1z, ISL85412eval1z evaluation boards? ? an1931 , ?isl85413demo1z, ISL85412demo1z wide vin synchronous buck regulator - short form? features ? wide input voltage range of 3.5v to 40v ? synchronous operation for high efficiency ? no compensation required ? integrated high-side and low-side nmos devices ? selectable pfm or forced pwm mode at light loads ? internal switching frequency 700khz ? continuous output current up to 150ma ?internal soft-start ? minimal external components required ? power-good and enable functions available applications ? industrial control ?medical devices ?portable instrumentation ? distributed power supplies ? cloud infrastructure figure 1. typical application figure 2. efficiency vs load, pfm, v in = 12v f sw = 700khz device must be connected to gnd plane with vias. max 150ma +3.5 ... +40v v out c5 1f l1 pg vin gnd r1 r2 c4 c1 20f u1 ISL85412 boot 2 vin 3 phase 4 en 5 pg 6 vcc 7 fb 8 mode 1 pgnd 9 gnd c8 vout c6 0.1f mode en 40 50 60 70 80 90 100 output load (a) efficiency (%) 1.0v out 1.2v out 1.5v out 2.5v out 3.3v out 1.8v out 5.0v out 0.00 0.03 0.06 0.09 0.12 0.15 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014, 2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. march 13, 2015 fn8378.1
ISL85412 2 fn8378.1 march 13, 2015 submit document feedback table of contents pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 efficiency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power-good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 pwm control scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 light load operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 protection features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 negative current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 over-temperature protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 boot undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 application guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 simplifying the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 output inductor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 buck regulator output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 package outline drawing . . . . . . . . . . . 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ISL85412 3 fn8378.1 march 13, 2015 submit document feedback pin configuration ISL85412 (8 ld 3x3 tdfn) top view pg vin vcc phase boot fb 1 2 3 4 8 7 6 5 en gnd mode pin descriptions pin # symbol pin description 1 mode mode selection pin. connect to logic high or vcc for pwm mode. connect to logic low or ground for pfm mode. logic ground enables the ic to automatically ch oose pfm or pwm operation. there is an internal 5m pull-down resistor to prevent an undefined logic state if mode is left floating. 2 boot floating bootstrap supply pin for the power mosfet gate driver. the bootstrap capacitor provides the necessary charge to turn on the internal n-channel mo sfet. connect an external 100nf capacitor from this pin to phase. 3 vin the input supply for the power stage of the regulator and the source for the internal linear bias regulator. place a minimum of 10f ceramic capacitance from vin to gnd and close to the ic for decoupling. 4 phase switch node output. it connects the switching fets with the external output inductor. 5 en regulator enable input. the regulator and bias ldo ar e held off when the pin is pulled to ground. when the voltage on this pin rises above 1v, the chip is enabled. connect this pin to vin for automatic start-up. do not connect en pin to vcc since the ldo is controlled by en voltage. 6 pg open drain power-good output that is pulled to ground when the output voltage is below regulation limits or during the soft-start interval. there is an internal 5m internal pull-up resistor. 7 vcc output of the internal 5v linear bias regulator. de couple to pgnd with a 1f ceramic capacitor at the pin. 8 fb feedback pin for the regulator. fb is the inverting input to the voltage loop error amplifier. comp is the output of the error amplifier. the output voltage is se t by an external resistor divider connected to fb. in addition, the pwm regulator?s power-good and uvlo circ uits use fb to monitor the regulator output voltage. epad gnd signal ground connections. connect to application board gnd plane with at least 5 vias. all voltage levels are measured with respect to this pin. the epad must not float. table 1. external component selection (refer to figure 1 ) v out (v) c 4 (pf) c 8 (f) l 1 (h) r 1 (k ) r 2 (k ) 1.0 100 2x22 10 90.9 137 1.2 100 2x22 10 90.9 90.9 1.5 100 2x22 16 90.9 60.4 1.8 100 2x22 16 90.9 45.3 2.5 100 22 22 90.9 28.7 3.3 100 22 33 90.9 20.0 5.0 100 22 47 90.9 12.4 12.0 100 22 100 90.9 4.75
ISL85412 4 fn8378.1 march 13, 2015 submit document feedback functional block diagram gate drive and deadtime bias ldo oscillator pfm current set fault logic 450mv/t slope compensation (pwm only) 930mv/a current sense pwm/pfm select logic zero current detection pwm pwm 600mv vref 150k 54pf internal compensation s r q q power- good logic fb internal = 50s 5m 5m pgnd phase boot vcc vin en fb mode pg gnd package paddle en/soft- start fb part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # ISL85412frtz 5412 -40 to +125 8 ld tdfn l8.3x3h ISL85412eval1z evaluation board ISL85412demo1z demonstration board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL85412 . for more information on msl please see techbrief tb363 .
ISL85412 5 fn8378.1 march 13, 2015 submit document feedback absolute maximum rating s thermal information vin to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +43v phase to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vin + 0.3v (dc) phase to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2v to 44v (20ns) en to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +43v boot to phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.5v comp, fs, pg, mode, ss, vcc to gnd. . . . . . . . . . . . . . . . . . -0.3v to +5.9v fb to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +2.95v junction temperature range at 0a . . . . . . . . . . . . . . . . . . . . . . . . . .+150c esd rating human body model (tested per jesd22-a114) . . . . . . . . . . . . . . . .2.5kv charged device model (tested per jesd22-c101e). . . . . . . . . . . . . . 1kv machine model (tested per jesd22-a115). . . . . . . . . . . . . . . . . . . . 200v latch-up (tested per jesd-78a; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance ? ja (c/w) ? jc (c/w) tdfn package ( note 4 , 5 ) . . . . . . . . . . . . . . 47 4 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c operating junction temperature range . . . . . . . . . . . . . .-40c to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5v to 40v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications t j = -40c to +125c, v in = 3.5v to 40v, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the junction temperature range. parameter symbol test conditions min ( note 8 )typ max ( note 8 units supply voltage v in voltage range v in 3.5 40 v v in quiescent supply current i q v fb = 0.7v, mode = 0v 50 a v in shutdown supply current i sd en = 0v, v in = 40v ( note 6 )1.8 2.5 a v cc voltage v cc v in = 40v 4.5 5.1 5.5 v v in = 12v; i out = 0a to 10ma 4.35 5 5.45 v power-on reset v cc por threshold rising edge 3.3 3.46 v falling edge 2.76 3v oscillator nominal switching frequency f sw f sw = v cc 600 700 784 khz minimum off-time t off v in = 3.5v 130 ns minimum on-time t on ( note 9 )90ns error amplifier error amplifier transconductance gain gm 50 a/v fb leakage current v fb = 0.6v 1 100 na current sense amplifier gain r t 0.84 0.93 1.02 v/a fb voltage t a = -40c to +125c 0.589 0.599 0.606 v power-good lower pg threshold - vfb rising 91 94 % lower pg threshold - vfb falling 81.5 85 % upper pg threshold - vfb rising 118 121 % upper pg threshold - vfb falling 107 111 % pg propagation delay percentage of the soft-start time 10 % pg low voltage i sink = 3ma, en = v cc , v fb = 0v 0.05 0.3 v
ISL85412 6 fn8378.1 march 13, 2015 submit document feedback tracking and soft-start internal soft-start ramp time en/ss = v cc 1.5 2.3 3.1 ms fault protection thermal shutdown temperature t sd rising threshold 150 c t hys hysteresis 20 c current limit blanking time t ocon 17 clock pulses overcurrent and auto restart period t ocoff 8 ss cycle positive peak current limit iplimit ( note 7 ) 0.36 0.4 0.44 a pfm peak current limit i pk_pfm 0.17 0.22 0.27 a zero cross threshold 5ma negative current limit inlimit ( note 7 ) -0.33 -0.30 -0.27 a power mosfet high-side r hds i phase = 100ma, v cc = 5v 900 1300 m low-side r lds i phase = 100ma, v cc = 5v 500 800 m phase leakage current en = phase = 0v 50 300 na phase rise time t rise v in = 40v 10 ns en/mode mode input threshold ris ing edge, logic high 1.3 1.45 v falling edge, logic low 0.4 1.0 v en threshold rising edge, logic high 1.2 1.45 v falling edge, logic low 0.4 0.9 v en logic input leakage current en = 0v/40v -0.5 0.5 a mode logic input leakage current mode = 0v 10 100 na mode pull-down resistor 5 6.15 m notes: 6. test condition: v in = 40v, fb forced above regulation point (0.6v), no switch ing, and power mosfet gate charging current not included. 7. established by both current sense amplifier gain test and current sense amplifier output test at i l = 0a. 8. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. 9. minimum on-time required to maintain loop stability. electrical specifications t j = -40c to +125c, v in = 3.5v to 40v, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the junction temperature range. (continued) parameter symbol test conditions min ( note 8 )typ max ( note 8 units
ISL85412 7 fn8378.1 march 13, 2015 submit document feedback efficiency curves f sw = 700khz, t a = +25c, c in = 20f figure 3. efficiency vs load, pfm, v in = 5v figure 4. efficiency vs load, pwm, v in = 5v figure 5. efficiency vs load, pfm, v in = 12v figure 6. efficiency vs load, pwm, v in = 12v figure 7. efficiency vs load, pfm, v in = 24v figure 8. efficiency vs load, pwm, v in = 24v 0 0.03 0.06 0.09 0.12 0.15 output load (a) efficiency (%) 40 50 60 70 80 90 100 1.5v out 2.5v out 3.3v out 1.8v out 1.2v out 1.0v out output load (a) efficiency (%) 40 50 60 70 80 90 100 2.5v out 0 0.030.060.090.120.15 1.8v out 1.2v out 1.0v out 1.5v out 3.3v out 40 50 60 70 80 90 100 output load (a) efficiency (%) 1.0v out 1.2v out 1.5v out 2.5v out 3.3v out 1.8v out 5.0v out 0 0.030.060.090.120.15 40 50 60 70 80 90 100 output load (a) efficiency (%) 1.5v out 3.3v out 1.8v out 5.0v out 0 0.03 0.06 0.09 0.12 0.15 1.0v out 1.2v out 2.5v out 40 50 60 70 80 90 100 1.0v out 1.2v out 1.5v out 12v out output load (a) efficiency (%) 0 0.03 0.06 0.09 0.12 0.15 2.5v out 1.8v out 3.3v out 5.0v out 40 50 60 70 80 90 100 12v out output load (a) efficiency (%) 0 0.03 0.06 0.09 0.12 0.15 2.5v out 1.8v out 5.0v out 1.5v out 1.0v out 1.2v out
ISL85412 8 fn8378.1 march 13, 2015 submit document feedback figure 9. efficiency vs load, pfm, v in = 36v figure 10. efficiency vs load, pwm, v in = 36v figure 11. v out regulation vs load, v out = 1v figure 12. v out regulation vs load, v out = 1.2v figure 13. v out regulation vs load, pwm, v out = 1.5v figure 14. v out regulation vs load, v out = 1.8v efficiency curves f sw = 700khz, t a = +25c, c in = 20f (continued) 40 50 60 70 80 90 100 12v out output load (a) efficiency (%) 0 0.03 0.06 0.09 0.12 0.15 2.5v out 1.8v out 5.0v out 1.5v out 1.2v out 3.3v out 40 50 60 70 80 90 100 12v out output load (a) efficiency (%) 0 0.03 0.06 0.09 0.12 0.15 1.8v out 5.0v out 3.3v out 1.5v out 2.5v out 1.2v out 0.990 0.995 1.000 1.005 1.010 1.015 1.020 0 0.030.060.090.120.15 output load (a) output voltage (v) 5v in pfm 5v in pwm 24v in pwm 24v in pfm 12v in pfm 12v in pwm 1.17 1.18 1.19 1.20 1.21 1.22 1.23 0 0.030.060.090.120.15 output load (a) output voltage (v) 12v in pwm 5v in pfm 5v in pwm 36v in pwm 24v in pfm 12v in pfm 36v in pfm 1.47 1.49 1.50 1.52 1.53 1.55 1.56 0 0.03 0.06 0.09 0.12 0.15 output load (a) output voltage (v) 5v in pwm 24v in pfm 12v in pfm 24v in pwm 5v in pfm 36v in pfm 36v in pwm 12v in pwm 1.77 1.78 1.79 1.80 1.81 1.82 1.83 0 0.030.060.090.120.15 output load (a) output voltage (v) 5v in pwm 24v in pfm 12v in pfm 24v in pwm 5v in pfm 36v in pfm 36v in pwm 12v in pwm
ISL85412 9 fn8378.1 march 13, 2015 submit document feedback figure 15. v out regulation vs load, v out = 2.5v figure 16. v out regulation vs load, v out = 3.3v figure 17. v out regulation vs load, v out = 5v figure 18. v out regulation vs load, v out = 12v efficiency curves f sw = 700khz, t a = +25c, c in = 20f (continued) 2.49 2.50 2.51 2.52 2.53 2.54 2.55 0 0.03 0.06 0.09 0.12 0.15 output load (a) output voltage (v) 5v in pwm 24v in pfm 12v in pfm 24v in pwm 5v in pfm 36v in pfm 36v in pwm 12v in pwm 3.29 3.30 3.31 3.32 3.33 3.34 3.35 0 0.03 0.06 0.09 0.12 0.15 output load (a) output voltage (v) 5v in pwm 24v in pfm 12v in pfm 24v in pwm 5v in pfm 36v in pfm 36v in pwm 12v in pwm 4.95 4.97 4.98 5.00 5.01 5.03 5.04 0 0.03 0.06 0.09 0.12 0.15 output load (a) output voltage (v) 24v in pfm 12v in pfm 24v in pwm 36v in pfm 36v in pwm 12v in pwm 11.90 11.98 12.05 12.13 12.20 12.28 12.35 0 0.03 0.06 0.09 0.12 0.15 output load (a) output voltage (v) 24v in pfm 24v in pwm 36v in pfm 36v in pwm
ISL85412 10 fn8378.1 march 13, 2015 submit document feedback typical performance curves v in = 12v, v out = 3.3v, f sw = 700khz, t a = +25c, c in = 20f, c out = 22f. figure 19. start-up at no load, pfm figure 20. start-up at no load, pwm figure 21. shutdown in no load, pfm figure 22. shutdown at no load, pwm figure 23. start-up at 150ma, pwm f igure 24. shutdown at 150ma, pwm phase 10v/div v out 2v/div ven 10v/div pg 5v/div 1ms/div v out 2v/div ven 10v/div pg 5v/div 1ms/div phase 10v/div v out 2v/div ven 10v/div pg 5v/div 100ms/div phase 10v/div v out 2v/div ven 10v/div pg 5v/div 100ms/div phase 10v/div 1ms/div v out 2v/div ven 10v/div pg 5v/div phase 10v/div 2ms/div v out 2v/div ven 10v/div pg 5v/div phase 10v/div
ISL85412 11 fn8378.1 march 13, 2015 submit document feedback figure 25. start-up at 150ma, pfm figure 26. shutdown at 150ma, pfm figure 27. start-up v in at 150ma load, pfm figure 28. start-up v in at 150ma load, pwm figure 29. shutdown v in at 150ma load, pfm figure 30. shutdown v in at 150ma load, pwm typical performance curves v in = 12v, v out = 3.3v, f sw = 700khz, t a = +25c, c in = 20f, c out = 22f. (continued) v out 2v/div ven 10v/div pg 5v/div phase 10v/div 1ms/div v out 2v/div ven 10v/div pg 5v/div phase 10v/div 5ms/div v out 1v/div pg 5v/div 1ms/div v in 10v/div i l 100ma/div v out 2v/div pg 5v/div 1ms/div v in 10v/div i l 100ma/div v out 2v/div pg 5v/div 5ms/div v in 10v/div i l 100ma/div v out 2v/div pg 5v/div 5ms/div v in 10v/div i l 100ma/div
ISL85412 12 fn8378.1 march 13, 2015 submit document feedback figure 31. start-up v in at no load, pfm figure 32. start-up v in at no load, pwm figure 33. shutdown v in at no load, pfm figure 34. shutdown v in at no load, pwm figure 35. jitter at no load, pwm f igure 36. jitter at full load, pwm typical performance curves v in = 12v, v out = 3.3v, f sw = 700khz, t a = +25c, c in = 20f, c out = 22f. (continued) v out 2v/div pg 5v/div 1ms/div phase 10v/div v in 10v/div 1ms/div v out 2v/div pg 5v/div phase 10v/div v in 10v/div v out 1v/div pg 5v/div phase 10v/div v in 5v/div 100ms/div 100ms/div v out 2v/div pg 5v/div phase 10v/div v in 10v/div phase 1v/div 100ns/div 100ns/div phase 1v/div
ISL85412 13 fn8378.1 march 13, 2015 submit document feedback figure 37. steady state at no load, pfm figure 38. steady state at no load, pwm figure 39. steady state at 150ma load, pwm figure 40. steady state at 20ma load, pfm figure 41.load transient, pfm figure 42.load transient, pwm typical performance curves v in = 12v, v out = 3.3v, f sw = 700khz, t a = +25c, c in = 20f, c out = 22f. (continued) v out ripple 20mv/div 5ms/div phase 10v/div i l 100ma/div 1s/div v out ripple 20mv/div phase 10v/div i l 100ma/div 1s/div v out 20mv/div phase 10v/div i l 100ma/div 2s/div v out 20mv/div phase 10v/div i l 100ma/div v out ripple 100mv/div 200s/div i l 100ma/div 200s/div v out ripple 50mv/div i l 100ma/div
ISL85412 14 fn8378.1 march 13, 2015 submit document feedback figure 43. output short circuit figure 44. overcurrent protection figure 45. pfm to pwm transition fi gure 46. pwm to pfm transition figure 47. overvoltage protection fi gure 48. overtemperature protection typical performance curves v in = 12v, v out = 3.3v, f sw = 700khz, t a = +25c, c in = 20f, c out = 22f. (continued) 20s/div v out 2v/div phase 10v/div i l 500ma/div pg 5v/div 10ms/div v out 2v/div phase 10v/div i l 500ma/div pg 5v/div 10s/div v out1 ripple 20mv/div phase1 10v/div i l 50ma/div 5s/div v out1 ripple 20mv/div phase1 10v/div i l 50ma/div 10s/div v out 2v/div phase 10v/div i l 200ma/div pg 5v/div 200ms/div v out 2v/div pg 2v/div
ISL85412 15 fn8378.1 march 13, 2015 submit document feedback detailed description the ISL85412 combines a synchronous buck pwm controller with integrated power switches. the buck controller drives internal high-side and low-side n-channel mosfets to deliver load current up to 150ma. the buck regulator can operate from an unregulated dc source, such as a battery, with a voltage ranging from +3.5v to +40v. an in ternal ldo provides bias to the low voltage portions of the ic. peak current mode control is utilized to simplify feedback loop compensation and reject input volt age variation. user selectable internal feedback loop compensa tion further simplifies design. the ISL85412 switches at a default 700khz. the buck regulator is equipped with an internal current sensing circuit and the peak current limi t threshold is typically set at 0.4a. power-on reset the ISL85412 automatically initializes upon receipt of the input power supply and continually monitors the en pin state. if en is held below its logic rising threshol d, the ic is held in shutdown and consumes typically 1.8a from the vin supply. if en exceeds its logic rising threshold, the regulator will enable the bias ldo and begin to monitor the vcc pin voltage. when the vcc pin voltage clears its rising por threshold, the controller will initialize the switching regulator circuits. if vcc never clears the rising por threshold, the controller will no t allow the switching regulator to operate. if vcc falls below its falling por threshold while the switching regulator is operating, the switching regulator will be shut down until vcc returns. soft-start to avoid large inrush current, v out is slowly increased at start-up to its final regulated value in 2.3ms. power-good pg is the open-drain output of a window comparator that continuously monitors the buck regulator output voltage via the fb pin. pg is actively held low when en is low and during the buck regulator soft-start period. after the soft-start period completes, pg becomes high impedance provided the fb pin is within the range specified in the ?electrical specifications? on page 5 . should fb exit the specified window, pg will be pulled low until fb returns. over-tempera ture faults also force pg low until the fault condition is cleare d by an attempt to soft-start. there is an internal 5m internal pull-up resistor. pwm control scheme the ISL85412 employs peak current-mode pulse-width modulation (pwm) control for fast transient response and pulse-by-pulse current limiting, as shown in the ? functional block diagram ? on page 4 . the current loop consists of the current sensing circuit, slope compen sation ramp, pwm comparator, oscillator and latch. current se nse transresistance is typically 930mv/a and slope compensation rate, se, is typically 450mv/t where t is the switching cycle period. the control reference for the current loop comes from the error amplifier?s output. a pwm cycle begins when a clock pulse sets the pwm latch and the upper fet is turned on. current begins to ramp up in the upper fet and inductor. this current is sensed (v csa ), converted to a voltage and summed with the slope compensation signal. this combined signal is compared to v comp and when the signal is equal to v comp , the latch is reset. upon latch reset the upper fet is turned off and the lower fet turned on allowing current to ramp down in the inductor. the lower fet will remain on until the clock initiates another pwm cycle. figure 49 shows the typical operating waveforms during the pwm operatio n. the dotted lines illustrate the sum of the current sense an d slope compensation signal. output voltage is regulated as the error amplifier varies its output and thus output inductor curr ent. the error amplifier is a transconductance type and its outp ut is terminated with a series rc (150k/54pf) network to gnd. the transconductance of the error amplifier is 50s. its noninverting input is internally connected to a 600mv reference voltage and its inverting input is connected to the output voltage via the fb pin and its associated divider network. light load operation at light loads, converter efficiency may be improved by enabling variable frequency operation (pfm ). connecting the mode pin to gnd will allow the controller to choose such operation automatically when the load current is low. figure 50 shows the pfm operation. the ic enters th e pfm mode of operation when 8 consecutive cycles of inductor current crossing zero are detected. this corresponds to a load current equal to 1/2 the peak-to-peak inductor ripple current and set by equation 1 : where d = duty cycle, f sw = switching frequency, l = inductor value, i out = output loading current, v out = output voltage. while operating in pfm mode, the regulator controls the output voltage with a simple comparat or and pulsed fet current. a comparator signals the point at which fb is equal to the 600mv reference at which time the regulator begins providing pulses of current until fb is moved above the 600mv reference by 1%. the current pulses are approximately 200ma and are issued at a frequency equal to the converter?s pwm operating frequency. figure 49. pwm operation waveforms v comp v csa duty cycle i l v out i out v out 1d C ?? 2lf sw ---------------------------------- - = (eq. 1)
ISL85412 16 fn8378.1 march 13, 2015 submit document feedback due to the pulsed current nature of pfm mode, the converter can supply limited current to the load. should load current rise beyond the limit, v out will begin to decline. a second comparator signals an fb voltage 1% lowe r than the 600mv reference and forces the converter to return to pwm operation. output voltage selection the regulator output voltage is easily programmed using an external resistor divider to scale v out relative to the internal reference voltage. the sc aled voltage is applied to the inverting input of the error amplifier; refer to figure 51 . the output voltage programming resistor, r 2 , depends on the value chosen for the feedback resistor, r 1 and the desired output voltage, v out , of the regulator. equation 2 describes the relationship between v out and resistor values. if the desired output voltage is 0.6v, then r 2 is left unpopulated and r 1 is 0 . protection features the ISL85412 is protected from overcurrent, negative overcurrent and over-temperature. the protection circuits operate automatically. overcurrent protection during pwm on-time, current through the upper fet is monitored and compared to a nominal 0.4a peak overcurrent limit. in the event that current reaches the limi t, the upper fet will be turned off until the next switching cycle. in this way, fet peak current is always well limited. if the overcurrent condition persists for 17 sequential clock cycles, the regulator will begin its hiccup sequence. in this case, both fets will be turned off and pg will be pulled low. this condition will be maintained for 8 soft-start periods after which the regulator will attempt a normal soft-start. should the output fault persist, the regulator will repeat the hiccup sequence indefinitely. there is no danger even if the output is shorted during soft-start. if v out is shorted very quickly, fb may collapse below 5/8 ths of its target value before 17 cycles of overcurrent are detected. the ISL85412 recognizes this condit ion and will begin to lower its switching frequency proportional to the fb pin voltage. this insures that under no circumstance (even with v out near 0v) will the inductor current run away. negative current limit should an external source somehow drive current into v out , the controller will attempt to regulate v out by reversing its inductor current to absorb the externally so urced current. in the event that the external source is low impedance, current may be reversed to unacceptable levels and the contro ller will initiate its negative current limit protection. similar to normal overcurrent, the negative current protection is re alized by monitoring the current through the lower fet. when the valley point of the inductor current reaches negative current limit, the lower fet is turned off and the upper fet is forced on until current reaches the positive current limit or an internal clock si gnal is issued. at this point, the lower fet is allowed to operate. should the current again be pulled to the negative limit on the next cycle, the upper fet will again be forced on and current will be forced to 1/6 th of the positive current limit. at this point the controller wi ll turn off both fets and wait for error amplifier?s output to indica te return to normal operation. during this time, the controller will apply a 100 load from phase to pgnd and attempt to discharge the output. negative current limit is a pulse-by-pulse style operation and recovery is automatic. negative current limit protection is disabled in pfm operating mode because reverse current is not allowed to build due to the diode emulation behavior of the lower fet. figure 50. pfm mode operation waveforms clock i l v out 0 8 cycles pwm pfm pwm load current pulse skip pfm r 2 r 1 x0.6v v out 0.6v C ---------------------------------- = (eq. 2) r 1 r 2 0.6v ea reference + - v out figure 51. external resistor divider fb
ISL85412 17 fn8378.1 march 13, 2015 submit document feedback over-temperature protection over-temperature protection limits maximum junction temperature in the ISL85412. when junction temperature (t j ) exceeds +150c, both fets are turned off and the controller waits for temperature to decrease by approximately 20c. during this time pg is pulled low. when temperature is within an acceptable range, the controller w ill initiate a normal soft-start sequence. for continuous operation, the +125c junction temperature rating should not be exceeded. boot undervoltage protection if the boot capacitor voltage falls below 1.8v, the boot undervoltage protection circuit will turn on the lower fet for 400ns to recharge the capacitor. this operation may arise during long periods of no switching such as pfm no load situations. in pwm operation near dropout (v in near v out ), the regulator may hold the upper fet on for multiple clock cycles. to prevent the boot capacitor from discharging, the lower fet is forced on for approximately 200ns every 34 clock cycles. application guidelines simplifying the design table 1 on page 3 provides component value selections for a variety of output voltages and will allow the designer to implement solutions with a minimum of effort. output inductor selection the inductor value determines the converter?s ripple current. choosing an inductor current re quires a somewhat arbitrary choice of ripple current, ? i . a reasonable starting point is 30% of total load current. the inductor value can then be calculated using equation 3 : increasing the value of inductan ce reduces the ripple current and thus, the ripple voltage. however, the larger inductance value may reduce the converter?s respon se time to a load transient. the inductor current rating should be such that it will not saturate in overcurrent conditions. for typical ISL85412 applications, inductor values generally lies in the 10h to 47h range. in general, higher v out will mean higher inductance. buck regulator output capacitor selection an output capacitor is required to filter the inductor current. the current mode control loop allows the use of low esr ceramic capacitors and thus supports ve ry small circuit implementations on the pc board. electrolytic and polymer capacitors may also be used. while ceramic capacitors offer excellent overall performance and reliability, the actual in-circuit capacitance must be considered. ceramic capacitors are rated using large peak-to-peak voltage swings and with no dc bias. in the dc/dc converter application, these conditio ns do not reflect reality. as a result, the actual capacitance ma y be considerably lower than the advertised value. consult the manufacturers data sheet to determine the actual in-application capacitance. most manufacturers publish capacitance vs dc bias so that this effect can be easily accommodated. the effects of ac voltage are not frequently published, but an assumption of ~20% further reduction will generally suff ice. the result of these considerations may mean an effective capacitance 50% lower than nominal and this value should be used in all design calculations. nonetheless, ceramic capacitors are a very good choice in many applications due to their reliability and extremely low esr. the following equations allow calculation of the required capacitance to meet a desired ripple voltage level. additional capacitance may be used. for the ceramic capacitors (low esr): where ? i is the inductor?s peak-to-peak ripple current, f sw is the switching frequency and c out is the output capacitor. if using electrolytic capacitors then: layout considerations proper layout of the power converter will minimize emi and noise and insure first pass success of the design. pcb layouts are provided in multiple formats on the intersil web site. in addition, figure 52 will make clear the important points in pcb layout. in reality, pcb layout of the ISL85412 is quite simple. a multi-layer printed circuit board with gnd plane is recommended. figure 52 shows the connections of the critical components in the converter. note that capacitors c in and c out could each represent multiple physical capacitors. the most critical connections are to tie the pgnd pin to the package gnd pad and then use vias to directly connect the gnd pad to the system gnd plane. this connection of the gnd pad to system plane insures a low impedance path for all return current, as well as an excellent thermal path to dissipate heat. with this connection made, place the high frequency mlcc input capacitor near the vin pin and use vias directly at the capacitor pad to tie the capacitor to the system gnd plane. the boot capacitor is easily placed on the pcb side opposite the controller ic and 2 vias directly connect the capacitor to boot and phase. place a 1f mlcc near the vcc pin and directly connect its return with a via to the system gnd plane. place the feedback divider close to the fb pin and do not route any feedback components near phase or boot. (eq. 3) l v in v out C f s ? i ? ------------------------------- - v out v in --------------- - ? = v outripple ? i 8 ? f sw ? c out ------------------------------------ - = (eq. 4) v outripple ? i*esr = (eq. 5)
ISL85412 18 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8378.1 march 13, 2015 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support. figure 52. printed circuit boar d power planes and islands revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change march 13, 2015 fn8378.1 upgraded the max nom vin from 36v to 40v and abs max to 43v. - on page 1 - changed all "36v" occurrences on to " 40v" and also changed "36v" to "40v" in the typical application diagram. - on page 5 - changed in the abs max ratings: "42v" to "43v" (twice) and "43v" to "44v" (once) and in the recommended operating conditions "36v" to "40v". on pages 5 and 6 - in the ec table, changed "36v" to "40v" all occurrences . - on page 15 - changed the occurrence "36v" to "40v" in the "detailed description". april 11, 2014 fn8378.0 initial release.
ISL85412 19 fn8378.1 march 13, 2015 submit document feedback package outline drawing l8.3x3h 8 lead thin dual flat no-lead plastic package (tdfn) rev 0, 2/08 bottom view top view side view detail x typical recomme nded land pattern located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be measured between 0.15mm and 0.30mm from the terminal tip. lead width dimension applies to the metallized terminal and is dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 8 5 1 4 see detail "x" 0 .80 max ( 6x 0 . 5 ) 2 . 80 ( 2.38 ) 8x 0.60 seating plane c 0.2 ref 0 . 05 max. 0 . 00 min. c 0.08 base plane c 0.10 c pin #1 index area 6 (4x) 0.15 pin 1 index area 3.00 b 3.00 a 6 6 x 0.50 8 x 0.25 c 0.10 m b a 8 x 0.40 1.50 ref ( 1.64 ) 2.38 1.64 2.20 ( 8x 0.25 ) ( 2 .20 )

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